1. Field of the Invention
This invention pertains to integrated circuit manufacture. More particularly, it relates to memory circuits which involve dynamic RAM (random access memory) cells, and especially to a testing method and structure for leakage current characterization in the manufacture of such memory cells.
2. Background Information
It is well known to provide FET (field effect transistor) memories in which the memory or storage cell consists of a capacitor storage element gated by a single FET. For example, commonly assigned U.S. Pat. No. 3,387,286 to Dennard discloses such a memory. The outstanding advantage of the FET memory of Dennard is that the integrated circuit structure can be fabricated, because of the simplicity of the cell, such that the substrate or wafer area required for each cell is extremely small. Consequently, a very large memory, including many cells, can be built on a single substrate. The memory, therefore, can be operated at extremely high speeds. However, the type of storage is not permanent because the stored charge, which defines a memory bit, tends to leak off over time, although the time during which the charge remains at a satisfactory value has been found to be relatively long compared with the read-write cycle time for the memory.
Accordingly, it is of critical importance in the production of such memories to be able to test effectively during the manufacturing process so that the completed cells will be characterized by a minimum time period requirement for periodically regenerating or refreshing their stored information. It will be understood that the time requirement is a function of the inherent leakage characteristic of the memory cell. Moreover, as will be appreciated, leakage currents play a very significant role as the individual cells become very small. An important criterion then in manufacturing such memories or systems is to determine accurately the various components of significant leakage currents that are contributed (1) by material defects or (2) by defects arising due to the nature of the particular process or technology adopted for fabricating these integrated circuit memories.
It is, therefore, a primary object of the present invention to provide a means for precisely determining the individual defects contributing to total leakage current, and for controlling same.
Another reference that may be found useful as background information in connection with the present invention is the integrated circuit structure described in U.S. Pat. No. 3,811,076 assigned to the assignee of the present application. That patent is pertinent because it discloses the notion of forming the capacitor, which is serially connected as the dynamic storage element to an FET, such that one of the capacitor electrodes corresponds with one of the conductivity-type regions of an FET electrode. That patent also discloses a polycrystalline silicon (polysilicon) field shield. Accordingly, this patent provides useful information with regard to the current or conventional method of fabricating field effect transistor memories.
More pertinent to the specific context of testing for leakage currents in integrated circuit memory fabrication is the disclosure in IBM TDB Volume 19, No. 3, August 1976, which describes a monitor circuit for leakage-sensitive FET devices. According to this monitor circuit, a pair of suitably connected FET devices enables measurement of very small leakage currents on standard parametric testers by a charge retention time technique. The described circuit also permits gate diffusion overlap capacitance to be measured; while the leakage distributions per wafer obtained by the described circuit furnishes an indication of the processing line quality.
Nevertheless, despite the teachings of the several references cited, there is nothing disclosed therein which enables the unique results achievable by the present invention to be fulfilled.
Accordingly, it is another primary object of the present invention to provide a method and a testing structure which will permit the characterization and isolation of particular leakage current components that are required to be measured in the process of making integrated circuits and more especially, integrated circuit FET memories.
A specific object is to create a memory diagnostic probe or testing device for separating the area-derived component of leakage from the isolation-bounded perimeter component of leakage in such manufacture.
Another object of the present invention is to provide a testing structure that will fit so-called "kerf" dimensional requirements which is important when the mix between the product and test site chip is low.
It should be explained in connection with the immediately above stated object that it has been proposed heretofore that, rather than taking up the space required for a normal chip for the purposes of testing, a testing site be developed in the kerf region (which is the region destroyed in the dicing operation when the wafer or substrate is cut up into the aforenoted chips). However, heretofore this has been impracticable because with the other testing means or techniques that have been suggested, such as retention time tests and the like, a requirement is imposed that a full-blown sense amplifier be provided on the test site. Consequently, in such a situation the area required becomes prohibitive. Likewise, other varieties of testing techniques have demanded that full-blown sense amplifiers be included as part of the testing device or structure.
Accordingly, it is a further object to provide a testing structure that takes up such a limited amount of area on a chip that on-chip amplification can be provided. Thus, a simple source follower for amplification purposes can be included on the test site, even within the "kerf" dimensions, whereby as much information can be obtained as would be obtained normally from a so-called "gated diode" of much larger area.
A further object is to provide a testing technique that lends itself to computerized analysis in determining and separating leakage current components. A direct result is that a good statistical sample on the wafer is practical with minimal product sacrifice due to lost area.
Still another object is to separate the aforenoted leakage current components on the same device or structure, so that all other variables are controlled but the one of immediate concern. Tests can be made to show the "goodness" of each part in sequence.
It is yet another object of the invention to provide a method and structure that will be a suitable vehicle for measuring other leakage such as bulk diffusion leakage at elevated temperature.